Test-Device für EMV-Konformitätstest

The IO-Link Interface Specification V1.1.3 defines a specific Test Device (see Appendix H.2.2 Test of a Master) that shall be connected to an IO-Link Master during the execution of EMC tests.

Functional Description

The device generates an 8-bit random number which is read out by the master. During the test the master shall return this random number to the device in the next IO-Link cycle.

The device checks whether it receives the correct random number and increments an internal error counter if not. The error counter is also incremented if a checksum error or a parity error is detected on the Device side.

The error count can be read out by the Master via an IO-Link parameter after the test. In addition, the error counter value is displayed by a 7-segment indicator.

When an error is detected, the Device generates a trigger signal to an optical output. A trigger box that converts the optical signal into a trigger pulse can be connected to the device. The trigger pulse supports developers in identifying possible issues on the Master side.

The Device can be configured to operate in one of 3 COM-speeds by DIP-Switches or by IO-Link Parameters.

EMC Test Device Features

  • Device fully compliant to V1.1.3 IO-Link Interface Specification
  • All 3 COM-Speeds supported (via Switch Selector and IO-Link Parameter)
  • Internal Pseudo-Random-Number Generators
  • Error counter for Parity, Checksum, Data and Time-out Errors
  • 7-Segment Error Counter Display
  • 7-Segment Device Status Display
  • Error Counter accessible via IO-Link
  • Optical Error Trigger Output
  • Additional support of round-trip delay measurements
  • Total error counts and maximum error counts within standardized group of M-Sequences separately available via IO-Link. Two group sizes selectable per COM-Speed


  • Better time-to-market
  • Identification of EMC issues

This website uses cookies. Usage of the website implies acceptance of cookies. Privacy information